Patterson D.A., Hennessy J.L.- Computer Organization and Design RISC-V Edition: The Hardware Software Interface (2nd edition) [2020, EPUB, ENG]

Cover image
Title page
Table of Contents
How to Use
Copyright
Dedication
Preface
1. Computer Abstractions and Technology
   1.1. Introduction
   1.2. Seven Great Ideas in Computer Architecture
   1.3. Below Your Program
   1.4. Under the Covers
   1.5. Technologies for Building Processors and Memory
   1.6. Performance
   1.7. The Power Wall
   1.8. The Sea Change: The Switch from Uniprocessors to Multiprocessors
   1.9. Real Stuff: Benchmarking the Intel Core i7
   1.10. Going Faster: Matrix Multiply in Python
   1.11. Fallacies and Pitfalls
   1.12. Concluding Remarks
   1.13. Historical Perspective and Further Reading
    Historical Perspective and Further Reading
2. Instructions: Language of the Computer
   2.1. Introduction
   2.2. Operations of the Computer Hardware
   2.3. Operands of the Computer Hardware
   2.4. Signed and Unsigned Numbers
   2.5. Representing Instructions in the Computer
   2.6. Logical Operations
   2.7. Instructions for Making Decisions
   2.8. Supporting Procedures in Computer Hardware
   2.9. Communicating with People
   2.10. RISC-V Addressing for Wide Immediates and Addresses
   2.11. Parallelism and Instructions: Synchronization
   2.12. Translating and Starting a Program
   2.13. A C Sort Example to Put it All Together
   2.14. Arrays versus Pointers
    Advanced Material: Compiling C and Interpreting Java
    Advanced Material: Compiling C and Interpreting Java
   2.16. Real Stuff: MIPS Instructions
   2.17. Real Stuff: ARMv7 (32-bit) Instructions
   2.18. Real Stuff: ARMv8 (64-bit) Instructions
   2.19. Real Stuff: x86 Instructions
   2.20. Real Stuff: The Rest of the RISC-V Instruction Set
   2.21. Going Faster: Matrix Multiply in C
   2.22. Fallacies and Pitfalls
   2.23. Concluding Remarks
    Historical Perspective and Further Reading
    Historical Perspective and Further Reading
3. Arithmetic for Computers
   3.1. Introduction
   3.2. Addition and Subtraction
   3.3. Multiplication
   3.4. Division
   3.5. Floating Point
   3.6. Parallelism and Computer Arithmetic: Subword Parallelism
   3.7. Real Stuff: Streaming SIMD Extensions and Advanced Vector Extensions in x86
   3.8. Going Faster: Subword Parallelism and Matrix Multiply
   3.9. Fallacies and Pitfalls
   3.10. Concluding Remarks
    Historical Perspective and Further Reading
    Historical Perspective and Further Reading
4. The Processor
   4.1. Introduction
   4.2. Logic Design Conventions
   4.3. Building a Datapath
   4.4. A Simple Implementation Scheme
    A Multicycle Implementation
    A Multicycle Implementation
   4.6. An Overview of Pipelining
   4.7. Pipelined Datapath and Control
   4.8. Data Hazards: Forwarding versus Stalling
   4.9. Control Hazards
   4.10. Exceptions
   4.11. Parallelism via Instructions
   4.12. Putting It All Together: The Intel Core i7 6700 and ARM Cortex-A53
   4.13. Going Faster: Instruction-Level Parallelism and Matrix Multiply
    Advanced Topic: An Introduction to Digital Design Using a Hardware Design Language to Describe and Model a Pipeline and More Pipelining Illustrations
   4.15. Fallacies and Pitfalls
   Advanced Topic: An Introduction to Digital Design Using a Hardware Design Language to Describe and Model a Pipeline and More Pipelining Illustrations
   4.16. Concluding Remarks
    Historical Perspective and Further Reading
    Historical Perspective and Further Reading
5. Large and Fast: Exploiting Memory Hierarchy
   5.1. Introduction
   5.2. Memory Technologies
   5.3. The Basics of Caches
   5.4. Measuring and Improving Cache Performance
   5.5. Dependable Memory Hierarchy
   5.6. Virtual Machines
   5.7. Virtual Memory
   5.8. A Common Framework for Memory Hierarchy
   5.9. Using a Finite-State Machine to Control a Simple Cache
   5.10. Parallelism and Memory Hierarchy: Cache Coherence
    Parallelism and Memory Hierarchy: Redundant Arrays of Inexpensive Disks
    Parallelism and Memory Hierarchy: Redundant Arrays of Inexpensive Disks
    Advanced Material: Implementing Cache Controllers
    Advanced Material: Implementing Cache Controllers
   5.13. Real Stuff: The ARM Cortex-A8 and Intel Core i7 Memory Hierarchies
   5.14. Real Stuff: The Rest of the RISC-V System and Special Instructions
   5.15. Going Faster: Cache Blocking and Matrix Multiply
   5.16. Fallacies and Pitfalls
   5.17. Concluding Remarks
    Historical Perspective and Further Reading
    Historical Perspective and Further Reading
6. Parallel Processors from Client to Cloud
   6.1. Introduction
   6.2. The Difficulty of Creating Parallel Processing Programs
   6.3. SISD, MIMD, SIMD, SPMD, and Vector
   6.4. Hardware Multithreading
   6.5. Multicore and Other Shared Memory Multiprocessors
   6.6. Introduction to Graphics Processing Units
   6.7. Domain-Specific Architectures
   6.8. Clusters, Warehouse Scale Computers, and Other Message-Passing Multiprocessors
   6.9. Introduction to Multiprocessor Network Topologies
    Communicating to the Outside World: Cluster Networking
    Communicating to the Outside World: Cluster Networking
   6.11. Multiprocessor Benchmarks and Performance Models
   6.12. Real Stuff: Benchmarking the Google TPUv3 Supercomputer and an NVIDIA Volta GPU Cluster
   6.13. Going Faster: Multiple Processors and Matrix Multiply
   6.14. Fallacies and Pitfalls
   6.15. Concluding Remarks
    Historical Perspective and Further Reading
    Historical Perspective and Further Reading
Appendix
   APPENDIX A. The Basics of Logic Design
   Index
APPENDIX B. Graphics and Computing GPUs
APPENDIX C. Mapping Control to Hardware
APPENDIX D. Survey of Instruction Set Architectures
Reference Data
Answers to Check Yourself
Glossary
Further Reading